Twin MONOS cell fabrication method and array organization

US6707079B2 · kind B2 · utility

Assignee

• Halo LSI, Inc. · US

Inventors

• Kumihiro Satoh · New York, US
• Seiki Ogura · Wappingers Falls, US
• Tomoya Saito · Tokyo, JP

Key dates

• Filing date: Feb 3, 2003
• Grant date: Mar 16, 2004
• Expiry date: Feb 3, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/954

Abstract

Presented in this invention is a fabricating method and its array organization for a high-density twin MONOS memory device integrating a twin MONOS memory cell array and CMOS logic device circuit. The invention consists of two fabrication methods,i) Simultaneous definition of memory gate and logic gate, thus improving the process integration scheme for easier and more reliable fabrication.ii) Bit line crosses word gate and control gate. The invention focuses on lowering parasitic sheet resistances to enable high speed while maintaining low manufacturing cost. The twin MONOS cell stores memory in two nitride memory cell elements underlying two shared control gates on both sidewalls of a select gate. The method is applicable to a device with a flat channel and/or a device having a step channel.Two embodiments of the present invention are disclosed.