Semiconductor leadframe for staggered board attach
US6707135B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2001 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Nov 21, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.