Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same
US6707153B2 · kind B2 · utility
45Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Apr 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device comprising a step of forming a plurality of resin layers, an interconnect connected electrically to an electrode of each of a plurality of semiconductor elements, and an external terminal connected electrically to the interconnect, on an aggregate of semiconductor elements having an electrode, and a step of cutting the aggregate, wherein at least one resin layer among the plurality of resin layers is formed avoiding a cutting region of the aggregate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.