Low power entry latch to interface static logic with dynamic logic
US6707318B2 · kind B2 · utility
11Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Mar 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.