CMOS sensor having analog delay line for image processing
US6707496B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/771
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to an analog delay line for a color CMOS image sensor which is compatible with MOS fabrication technology. The invention allows for the simultaneous reading of pixel signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained. The delay line includes a set of storage capacitors on which the pixel signals are stored, and a means for writing the signals from the pixels onto the capacitors in sequence. The stored analog pixel signals may then be read out from the delay line at the appropriate time so that they may be combined with pixel signals from adjacent pixels in different rows. In one embodiment, two delay lines are used, so that pixel signals from a current row can be written into one delay line, while the pixel signals from a previous row are being read out from the other delay line. In another embodiment, a single delay line is used in combination with a single pixel delay circuit. When the single pixel delay circuit is used, the pixel signals from a previous row are read out from the delay line and temporarily stored in the single pixel delay circuit, one at a time, shortly after which the pi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.