Integrated dynamic memory device and method for operating an integrated dynamic memory
US6707705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions—to be performed for a memory access—from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.