Static random access memory with symmetric leakage-compensated bit line
US6707708B1 · kind B1 · utility
25Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Sep 10, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Sep 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.