Interface circuit with improved integration
US6708245B1 · kind B1 · utility
3Cited by
7References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 5, 1999 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6418
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some of the circuits for executing processes on the physical layer are accommodated in a first chip that includes a link layer circuit. More specifically, an arbiter circuit composed only of a logic circuitry and having a relatively large circuit scale, and state machines, built in a control circuit, are accommodated in the first chip in the form of a control signal generation circuit. The other portions of the physical layer circuit remains in the second chip. A higher degree of integration of the first chip results in a higher degree of integration of many of the circuitry for executing processes on the physical layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.