Semiconductor integrated circuit and data processing system
US6708249B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2002 |
| Grant date | Mar 16, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.