Contamination control for embedded ferroelectric device fabrication processes
US6709875B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 8, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.