Method of forming IC package having upward-facing chip cavity
US6709897B2 · kind B2 · utility
34Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.