Method of fabricating integrated system on a chip protection circuit
US6709900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/307
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.