Method for improving gate oxide integrity and interface quality in a multi-gate oxidation process
US6709932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
Abstract
One aspect of the invention relates to a method of manufacturing a multi-gate integrated circuit device. According to the method, a protective coating substantially prevents processes used to form a second gate dielectric from affecting a first gate dielectric. In an exemplary process, an oxide gate dielectric is grown for peripheral region transistors, a protective coating of silicon nitride is deposited over the peripheral region gate oxide, the oxide and protective coating are etched from a core region, and then a second oxide dielectric is grown for core region transistors while the silicon nitride coating substantially prevents further oxide growth in the peripheral region. The protective coating can also prevent nitridation of the core region gate dielectric from affecting the peripheral region gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.