Method for creating a damascene interconnect using a two-step electroplating process
US6709970B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming void-free, low contact-resistance damascene interconnects during a manufacturing process of an integrated circuit having both narrow and deep openings and wide and shallow openings on a same substrate features a two-step copper (Cu) deposition process, with a high-temperature rapid annealing process being conducted after the first deposition. After forming in a top surface a narrow and deep opening and a wide and shallow opening, a first copper (Cu) layer is deposited on a seed layer using a small-grained Cu material to completely fill the narrow and deep opening. After annealing the first Cu layer to reduce stress on the resulting structure, a second layer of large-grained Cu material is deposited on the annealed first Cu layer to fill the remainder of the openings. The resulting assembly, which requires no additional annealing, is then planarized to the original surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.