Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit
US6710425B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2001 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Apr 26, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/906
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure. Damascene processes are used to manufacture the multiple metal layer interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.