Distributed power device with dual function minority carrier reduction

US6710427B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Taylor R. Efland · Richardson, US
• David Alexander Grant · Edinburgh, GB
• Ramanathan Ramani · Plano, US
• Chin-Yu Tsai · Plano, US
• David D. Briggs · Richardson, US
• Dale J. Skelton · Plano, US

Key dates

• Filing date: Jun 11, 2002
• Grant date: Mar 23, 2004
• Expiry date: Jun 11, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/307
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the la…