Semiconductor device arrangement and method of fabricating the same
US6710435B2 · kind B2 · utility
17Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jul 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device arrangement includes a plurality of three-dimensional semiconductor units. Each of the three-dimensional semiconductor units includes a semiconductor chip in a shape of a rectangular parallelepiped having six surfaces, and semiconductor devices formed on at least one among the six surfaces. The three-dimensional semiconductor units are mechanically connected and supported, and are electrically connected in a suitable way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.