Wafer level packaging of micro electromechanical device
US6710461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Aug 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present invention provides a wafer level package of micro electromechanical devices. The wafer level package of the present invention comprises a wafer having a plurality of micro electromechanical devices and a package wafer of the same size. A plurality of conductor plugs penetrate through the upper and lower surfaces of the package wafer. Solder bumps are formed on the conductor plugs to be adhered to predetermined solder bumps on the micro electromechanical device wafer so as to form a package device. The wafer level package of the present invention can prevent micro electromechanical devices from damage during the packaging procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.