Refreshing of multi-port memory in integrated circuits
US6711081B1 · kind B1 · utility
7Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port memory module comprising a contention circuit for refresh in order to detect a conflict between an externally requested access and a refresh operation is described. The refresh operation is allocated to the port that is not externally accessed. When accesses through both ports are requested, a wait cycle for one of the access requests is inserted until the refresh is terminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.