Reducing digit equilibrate current during self-refresh mode
US6711093B1 · kind B1 · utility
9Cited by
8References
53Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.