4:2 compressor circuit for use in an arithmetic unit
US6711633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Sep 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.