Using a model specific register as a base I/O address register for embedded I/O registers in a processor
US6711673B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2000 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jan 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes an input/output (I/O) register that is mapped into input/output (I/O) address space. The processor also includes a base address register that is loaded with a base address. The base address register may be a model specific register (MSR). The input/output register is accessed with an input/output instruction at an address determined according to the base address and an offset therefrom. The base address register may be accessible to software operating at a high privilege level and not accessible to software operating at a lower privilege level, while the I/O register is accessible to software operating at the lower privilege level. The processor determines when an I/O access is to the processor I/O register and accesses that I/O register without causing an input/output bus cycle that would otherwise occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.