Method and apparatus for reducing power consumption in VLSI circuit designs

US6711719B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• John M. Cohn · South Burlington, US
• Alvar A. Dean · South Burlington, US
• Amir Farrahi · Peekskill, US
• David J. Hathaway · Underhill Center, US
• Thomas Lepsic · Jeffersonville, US
• Patrick E. Perry · South Burlington, US
• Scott A. Tetreault · Saint Albans, US
• Sebastian T. Ventrone · South Burlington, US

Key dates

• Filing date: Aug 13, 2001
• Grant date: Mar 23, 2004
• Expiry date: Jan 22, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In integrated circuit (IC) designs, a component of power consumed may be represented as Power=½ FCV2, where C is the load capacitance being driven by a source cell, F is the switching frequency of the source cell, and V is the total output voltage swing. However, not every signal value generated by a source cell is required to propagate to all the sink cells connected to the source for every clock cycle of a chip. Accordingly, an isolate cell is inserted in a net (wire) connecting a source cell to at least one sink cell, to de-couple the at least one sink cell and a portion of the net from the source cell when a signal output by the source need not propagate. Due to the de-coupling, the load capacitance associated with the at least one sink and net portion is not experienced by the source cell for such signals. Accordingly, overall IC power consumption is reduced.