Synthesizing signal net information from multiple integrated circuit package models
US6711730B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2002 |
| Grant date | Mar 23, 2004 |
| Priority date | — |
| Expiry date | Jun 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q40/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.