Method for manufacturing a multi-level interconnect structure
US6713835B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2003 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the mandrel material for each level of the interconnect structure. The conductive features in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.