Processor having an arithmetic extension of an instruction set architecture
US6714197B1 · kind B1 · utility
29Cited by
71References
61Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having an arithmetic extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to reduction add, reduction multiply, reciprocal, and reciprocal square root.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.