Write operation for capacitorless RAM
US6714436B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region (12). Data is written to the cell by the instigation of band-to-band tunneling (BTBT) and the resulting generation of hole/electron pairs. Electrons are drawn from the body region through forward-biased drain (14) and source (15) regions so that holes accumulate in the body region. The increase in threshold voltage, caused by the accumulation of holes, may be defined and detected as a logic level (ONE, for example). In one embodiment, a split biasing scheme applies substantially identical voltages to the drain and to the source and a negative bias to the gate. In alternative embodiments, a negative gate bias is not required and the drain and source bias voltages may be offset so as to mitigate source damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.