Method of programming a multi-level memory device
US6714448B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of programming a multi-level memory chip in which the first, or lowest, voltage memory state through the next-to-last voltage memory state are programmed by a plurality of programming pulses increasing incrementally in voltage, alternated with a plurality of verify pulses, and in which the last, or highest, voltage memory state of the memory cell is programmed with a programming pulse of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programming the intermediate memory states of the cell, while providing speed in programming the last memory state of the cell to increase the overall speed of the programming the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.