Flash memory including means of checking memory cell threshold voltages
US6714453B2 · kind B2 · utility
17Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.