Method and circuit for generating constant slew rate output signal
US6714462B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved output buffer having a substantially constant slew rate comprises a slew rate control circuit and an output driver circuit. The slew rate control circuit is configured at the input terminals of the output driver circuit to suitably control the slew rate of the input signal for the output driver circuit based on the level of voltage of a power supply for the output driver circuit. For increases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is decreased, while for decreases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is increased, such that the variation of the slew rate of the output signal of the output buffer is significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.