System for using rate of exception event generation during execution of translated instructions to control optimization of the translated instructions
US6714904B1 · kind B1 · utility
21Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1999 |
| Grant date | Mar 30, 2004 |
| Priority date | — |
| Expiry date | Oct 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for modifying operating conditions within a computer which translates instructions from a target instruction set to a host instruction set including the steps of monitoring an event occurring within a component of the computer, counting events occurring within a selected interval, generating an exception if a total of events within the selected interval exceeds a prescribed limit, and responding to the exception by modifying a translated sequence of host instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.