Spacer fabrication for flat panel displays
US6716081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.