Methods of making microelectronic assemblies using compressed resilient layer
US6716671B2 · kind B2 · utility
5Cited by
13References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a microelectronic assembly comprises providing a first side assembly juxtaposed with a second side assembly and a first resilient element disposed therebetween. Leads extend between the first side assembly and the second side assembly. A compressive force is applied to the juxtaposed assemblies so as to compress the first resilient element and the compressive force is at least partially released so as to allow the first resilient element to expand, thereby moving one or both of the first side assembly and the second side assembly to deform the leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.