Method of forming first level of metallization in DRAM chips
US6716764B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method of forming contacts and metal lands onto a semiconductor structure at the first level of metallization (M0). The initial structure is a silicon substrate having diffusion regions formed therein and a plurality of gate conductor stacks formed thereon. The structure is passivated by an insulating layer. Contact holes of a first type are etched in the insulating layer to expose some diffusion regions, then filled with doped polysilicon to form conductive studs substantially coplanar with the insulating layer surface. A first mask (M0) is formed at the surface of the structure to expose M0 land recess locations including above said studs. The masked structure is anisotropically dry etched to create M0 land recesses. Next, the M0 mask is removed. A second mask (CS) is formed at the surface of the structure to expose desired contact hole locations of a second type. The masked structure is again anisotropically dry etched to expose the diffusion regions and the top of gate conductor stacks. The CS mask is removed. Finally, said M0 land recesses and contact holes are filled with a metal, so that the metal and the insulating material top surface are substantially…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.