Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks

US6717221B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ian R. Post · Colorado Springs, US
• Kaizad Mistry · Lake Oswego, US

Key dates

• Filing date: Apr 30, 2003
• Grant date: Apr 6, 2004
• Expiry date: Apr 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

An apparatus including a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.