Analog to digital converter
US6717542B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a conversion sequence for converting an analog input voltage into a digital signal, a redundant comparison cycle is provided to comparison cycles for performing a prescribed number of times of comparison. This redundant comparison cycle may be added after the prescribed number of comparison cycles, or may be inserted into a normal comparison cycle. Such a redundant comparison cycle adds a convergence period of a converted value to the analog input voltage. Accordingly, the final conversion result can be accurately generated even if an error is generated in the conversion sequence. As a result, a successive approximation type analog to digital converter capable of rapidly performing analog-to-digital conversion with high accuracy is implemented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.