Deferred shading graphics pipeline processor having advanced features

US6717576B1 · kind B1 · utility

Assignee

• Apple Computer Inc. · US

Inventors

• Jerome F. Duluk, Jr. · Palo Alto, US
• Richard E. Hessel · Pleasanton, US
• Vaughn T. Arnold · Scotts Valley, US
• Jack Benkual · Cupertino, US
• Joseph P. Bratt · San Jose, US
• George Cuan · Sunnyvale, US
• Stephen L. Dodgen · Pullman, US
• Emerson S. Fang · Fremont, US
• Zhaoyu Gong · Cupertino, US
• Thomas Y. Ho · Milpitas, US
• Hengwei Hsu · Fremont, US
• Sidong Li · Zhanjiang, CN
• Sam Ng · Fremont, US
• Matthew Nicholas Papakipos · Palo Alto, US
• Jason Redgrave · Mountain View, US
• Sushma S. Trivedi · Sunnyvale, US
• Nathan Tuck · Corvallis, US
• Shun Wai Go · Cupertino, US
• Lindy Fung · Sunnyvale, US
• Tuan D. Nguyen · San Jose, US
• Joseph P. Grass · Menlo Park, US
• Bo Hong · Mountain View, US
• Abraham Mammen · Pleasanton, US
• Abbas Rashid · Fremont, US
• Albert Suan-Wei Tsay · Fremont, US

Key dates

• Filing date: Aug 20, 1999
• Grant date: Apr 6, 2004
• Expiry date: Aug 20, 2019

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/83
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.