Systems having modules with buffer chips
US6717823B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/1092
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, the invention includes a system having first and second modules, the first module having a first group of chips and the second module having a second group of chips, and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first buffer on the first module and a second buffer on the second module, and a path including conductors in a first section that splits into a second section and third section, wherein the second section couples to the first buffer and the third section couples to the second buffer, and wherein impedances of the second and third sections are at least 50% greater than impedances of the first section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.