Matchline sensing for content addressable memories
US6717876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2002 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Dec 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sense node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison. Reference matchlines are used to generate timed control signals for enabling the latch circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.