Cache memory and method of operation
US6718439B1 · kind B1 · utility
13Cited by
2References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Oct 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6082
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An N-way set associative virtual victim cache in which cache accesses are automatically directed only to the data array in the most recently used way. The cache memory comprises: 1) N ways, each of the N ways comprising a data array capable of storing L cache lines and a tag array capable of storing L address tags, each of the L address tags associated with one of the L cache lines; and 2) address decoding circuitry capable of receiving an incoming memory address and accessing a target cache line corresponding to the incoming memory address only in a most recently used one of the N ways.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.