Systems and methods for prefetch operations to reduce latency associated with memory access
US6718454B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.