Delay locked loop for an FPGA architecture
US6718477B1 · kind B1 · utility
26Cited by
8References
4Claims
0Family size
Inventors
Key dates
| Filing date | Mar 6, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Mar 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.