Precoders for partial response channels
US6718502B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03178
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Precoders and their corresponding logic schemes, together with a method of using the precoders and their schemes to generate a media code sequence of symbols for data storage channels, with partial response equalization and a multilevel encoding/modulation scheme. Partial responses are defined by the classical and modified target polynomials, while the multilevel encoding/modulation schemes include: 1) Structured Set Partitions (SSP), 2) a set of conventional block codes with different error correcting capabilities, and 3) a variety of iterative decoding such as the List Trellis Decoder (LTD), the BCJR algorithm, and soft decoding of low-density parity check codes. The precoders are derived from the SSP's, and combined with conventional ECC encoders designed for error detection, or error correction, or both. A cascade of parallel ECC encoders, followed by an SSP precoder, increases the minimum Euclidean distance between different media code sequences of symbols, and as a result gives lower bit error rates after decoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.