Method and system for measuring and reporting test coverage of logic designs
US6718521B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2000 |
| Grant date | Apr 6, 2004 |
| Priority date | — |
| Expiry date | Apr 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for easily and automatically determining the extent of test coverage for a design-under-test (DUT). Incremental test coverage information is gathered from the application of test cases to the DUT, and cumulative test coverage information is maintained. The incremental test coverage and cumulative test coverage information are fed into a correlation process, which correlates valid bus transactions automatically generated from a configuration file describing the DUT with the incremental and cumulative test coverage information. The correlation process determines which valid bus transactions have or have not been applied in testing the DUT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.