Low-K gate spacers by fluorine implantation
US6720213B1 · kind B1 · utility
250Cited by
10References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Jan 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.