Method for wafer test and wafer test system for implementing the method
US6720789B1 · kind B1 · utility
10Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Feb 24, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for testing wafers, and particularly a wafer test system employing probes to provide for electrical contact with a device under test (DUT) which is located on a wafer. More particularly, also provided is a method and system for implementing wafer tests where the probes first contact a simulated wafer which incorporates an array of spaced load cells to determine the optimum probe overdrive. The DUT is then tested at the optimum overdrive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.