Dual edge-triggered flip-flop design with asynchronous programmable reset
US6720813B1 · kind B1 · utility
28Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2003 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Mar 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.