Cache memory
US6721193B2 · kind B2 · utility
3Cited by
9References
50Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0895
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory and method for operating a cache memory are provided which comprise a tag RAM, tag RAM sense amplifier circuitry, data RAM sense amplifier circuitry and decision circuitry. Timing difficulties exist in determining whether or not a hit has occurred and in outputting the data from the data RAM upon occurrence of a hit. Upon addressing a tag entry and the corresponding data entry, the tag information is output from the tag RAM and is compared with input address information. A decision is reached as to whether or not identity exists. Only when the result of that decision has been validly determined can data be output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.