Integrated memory with memory cells in a plurality of memory cell blocks, and method of operating such a memory
US6721230B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Sep 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory including memory cells in a plurality of memory cell blocks, each memory cell block being assigned at least one dedicated data line and a register circuit that can be written from outside the memory. At the start of a test operation, data is stored in the register circuits as reference data. During an access cycle, in each case in each of the memory cell blocks, a respective memory cell or a group of memory cells is selected, a respective read amplifier is activated and, in each of the register circuits, a comparison between the data read out and the reference data is carried out. As a result, the time required for the test operation of the memory is made comparatively low.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.