Diagnosis of combinational logic circuit failures
US6721914B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2001 |
| Grant date | Apr 13, 2004 |
| Priority date | — |
| Expiry date | Jul 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/317
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.